1. Field of the Invention
This invention relates generally to methods for manufacturing electrical conductor lines or wiring for use in semiconductor integrated circuits. More particularly, it relates to an improved method for fabricating metal lines in multilevel VLSI semiconductor integrated circuit devices so as to reduce parasitic capacitance.
2. Description of the Prior Art
As is generally well-known in the semiconductor industry, there has existed a continuing trend of fabricating integrated circuits with extremely increased complexity and sophistication where literally millions and millions of active circuit devices are formed on or in a silicon substrate or well. The manufacturing of these complex, high-density, very-large-scale-integration (VLSI) semiconductor integrated circuits has been developed in part due to the advances made in integrated circuit fabrication technology where circuit components can now be made with dimensions on the order of sub-micron size. In addition, there has been developed new thin deposition technology which enables the formation of thin-films with precise composition and thickness at precisely defined locations.
Moreover, in order to maintain a relatively small die size, the VLSI semiconductor integrated circuit devices are typically fabricated with higher and higher densities by the process of using multilevel metal lines and metallized interconnect structures for connecting between the multiple levels. The multiple level layers of metal lines are generally separated by interlevel dielectrics (for example, silicon dioxide) electrically coupled by metal-filled vias provided at selected areas within the dielectric layers. The vias are filled with a plug and serve to make an electrical conduit between the different stacked multiple levels of the metal lines. The metal plug is typically formed of a refractory metal, such as tungsten.
In the stacked multiple levels, each of the metal line structures is formed using aluminum or aluminum alloys. However, since the interlevel dielectrics are being made with smaller and smaller thicknesses so as to accommodate the densely packed active circuits there will be created parasitic capacitance between one of the individual metal lines and the other remaining metal lines in the same level and in the other levels, thereby degrading the performance of the active circuits. In an article entitled "Use of Air Gap Structures To Lower Interlevel Capacitance" authored by J. G. Fleming and E. Roherty-Osmun of Sandia National Laboratories, there has been reported on the feasibility of creating an air gap between closely spaced metal lines so as to reduce interlevel capacitance, International DUMIC Conference, pp. 139-146, February, 1997.
Nevertheless, there still exists a need of a method for fabricating metal lines in multilevel VLSI semiconductor integrated circuit devices so as to reduce parasitic capacitance.
The present invention represents a significant improvement over the prior art techniques and thus provides a method for fabricating metal lines with decreased capacitance. This is achieved in the instant invention by performing an additional undercutting etching step so as to cut underneath the metal lines in order to form air voids thereafter.